Typically, a computer system includes a number of integrated circuit devices that communicate with one another to perform system applications. Often, the computer system includes a controller, such as a micro-processor, and one or more memory devices, such as random access memory (RAM) devices. The RAM can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), reduced latency DRAM (RLDRAM), pseudo static RAM (PSRAM), and low power DDR-SDRAM (LPDDR-SDRAM). PSRAM provides advantages in density and speed over traditional static RAM (SRAM).
Integrated circuit device speeds continue to increase and the amount of data communicated between devices continues to increase to meet the demands of system applications. As data volume increases, the industry continues to develop larger memory sizes to accommodate increased data requirements. These trends, of increasing data volume and larger memory sizes, are expected to continue into the future.
Some computer systems include mobile applications and have limited space resources. In mobile applications, such as cellular telephones and personal digital assistants (PDAs), memory cell density and memory device size are issues for future generations. To address these issues, the industry continues to develop higher density memory devices. In one type of memory device, referred to as a stacked component memory device, multiple memory die are packaged in a single package to achieve dramatic space reductions over standard packages and unprecedented memory density per board area. Typically, in these memory devices the memory die share most package pins in parallel, but include separate chip select pins for individually selecting each die.
During testing of stacked component memory devices, compression test mode and other design for test features can be used to compress all outputs of an individual memory die to one output pin. If input/output (I/O) pins from multiple die are connected together, the die cannot be tested in parallel since the tester comparator or judgment circuit cannot determine the outputs of an individual die.
Typically, an individual memory die is selected via its chip select pin and the other memory die in the package are deselected to disable the outputs of all memory die except the memory die under test. The target memory die is tested and the other memory die are sequentially tested using the same method. The total test time is the test time of one memory die times the number of memory die in the package. All the while there is increased pressure to lower the cost of testing and per unit cost. These challenges require test systems and methods that offer greater parallelism and configuration flexibility.
For these and other reasons there is a need for the present invention.